Generally, semiconductor devices include a plurality of circuits which form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
In semiconductor interconnect structures, electromigration (EM) has been identified as one metal failure mechanism. EM is one of the worst reliability concerns for very large scale integrated (VLSI) circuits. The problem not only needs to be overcome during the process development period in order to qualify the process, but it also persists through the lifetime of the chip. Voids are created inside the metal conductor of an interconnect structure due to metal ion movement caused by the high density of current flow.
Although the fast diffusion path in metal interconnects varies depending on the overall integration scheme and materials used for chip fabrication, it has been observed that metal atoms, such as Cu atoms, transported along the metal/post planarized dielectric cap interface play an important role on the EM lifetime projection. The EM initial voids first nucleate at the metal/dielectric cap interface and then grow in the direction of the bottom of the interconnect, which eventually results in a circuit dead opening.
FIGS. 1A-1D are pictorial representations of a prior art interconnect structure at various stages of EM failure. In these drawings, reference numeral 12 denotes the dielectric cap, and reference numeral 10 denotes the conductive feature typically comprised of Cu or some other conductive metal; all other components of the prior art interconnect structure are not labeled to avoid obscuring the EM problem. FIG. 1A is at an initial stress stage. FIG. 1B is at a time when void 14 nucleation initiates at the conductive feature 10/dielectric cap 12 interface. FIG. 1C is at a time when the void 14 grows toward the bottom of the conductive feature 10, and FIG. 1D is at a time in which the void 14 growth crosses the conductive feature 10 causing a circuit dead opening.
Although EM causes circuit dead openings and is unwanted in interconnect structures, electrically blowable fuses take advantage of the EM effect described above to open an electrical connection; a fuse is a structure, which can be broken down or blown in accordance with a suitable electrical current, which is provided through the fuse to provide an open circuit condition. Within the context of integrated circuitry memory devices, fuses can be used to program in redundant rows of memory. Fuses have use in other integrated circuitry applications as well.
During programming of fuse structures, voids form at the center of the fuse element due to high current density, and eventually causes the conductive material to pile-up and forms hillocks at the anode (most positive) end of the fuse element. Hillock formation is an undesirable effect that has not been exploited for any useful purposes in the prior art.
Despite the separate developments of interconnect structures and fuse structures, there is still a need for integrating both structures into a single structure such that the interconnect structure has a higher electromigration (EM) resistance as compared with the fuse structure. Also, there is a need for a semiconductor structure in which the higher EM resistant interconnect structure and the lower EM resistant fuse structure are formed within the same interconnect level.